A conventional main memory of a system generally includes a dynamic random access memory (DRAM). The DRAM is characterized by a simple structure and a high read speed. A basic memory cell of the DRAM is a DRAM cell, and each DRAM cell includes one transistor and one capacitor. The DRAM cell uses an amount of electricity stored in the capacitor to indicate 0 or 1. In this manner, one DRAM cell may store one bit. Because a capacitor is subject to electricity leakage, if electric charges in the capacitor are insufficient, stored data may suffer an error. Therefore, in an actual application, a capacitor needs to be charged periodically. By charging and discharging a capacitor, a DRAM cell can be read and written and thus be updated. In other words, the DRAM is periodically refreshed. In an actual application, DRAM cells in a DRAM are arranged and distributed into a matrix, and the matrix is referred to as a DRAM bank. Using corresponding row and column decoders, any bit in the DRAM bank can be located. Multiple DRAM banks may constitute one DRAM chip, multiple DRAM chips may constitute one DRAM rank, and multiple DRAM ranks may be further integrated into one dual in-line memory module (DIMM).
The Joint Electron Device Engineering Council (JEDEC) is a standardization organization in the solid-state and semiconductor industry. According to a memory-related standard released by the JEDEC, a DRAM is required to refresh every line at least once in 64 ms. In other words, a refresh cycle of the DRAM specified by the JEDEC is 64 ms. Therefore, currently, DRAMs are almost all manufactured in accordance with the refresh-per-64 ms standard that ensures no data loss. In an actual application, a DRAM controller is required to send a refresh instruction every 7.8 μs, and each instruction is responsible for refreshing one line or multiple lines in a DRAM bank, so as to ensure that all lines in a DRAM are refreshed in 64 ms. As a capacity of the DRAM grows and a quantity of lines increases, a quantity of lines that need to be refreshed by each refresh operation increases accordingly, and consequently, system power consumption also becomes higher. Therefore, as the capacity of the DRAM grows constantly, lowering a refresh frequency of the DRAM is crucial to reducing system power consumption. However, if a refresh cycle of the DRAM is lengthened for reducing system power consumption, an error may be caused to data in the memory.